Kerala PSC Previous Years Question Paper & Answer

Title : HEAD OF SECTION COMPUTER ENGINEERING TECHNICAL EDUCATION Medium of Question: English
Question Code : A

Page:8


Below are the scanned copy of Kerala Public Service Commission (KPSC) Question Paper with answer keys of Exam Name 'HEAD OF SECTION COMPUTER ENGINEERING TECHNICAL EDUCATION Medium of Question: English' And exam conducted in the year 2019. And Question paper code was '012/2019/OL'. Medium of question paper was in Malayalam or English . Booklet Alphacode was 'A'. Answer keys are given at the bottom, but we suggest you to try answering the questions yourself and compare the key along wih to check your performance. Because we would like you to do and practice by yourself.

page: 8 out of 12
Excerpt of Question Code: 012/2019/OL

C:-Synchronous

D:-Serial
Correct Answer:- Option-C
Question65:- is used to restore the contents of the cells in synchronous DRAM.

A:-Sense amplifier

B:-Refresh counter

C:-Restorer

D:-Restore counter

Correct Answer:- Option-A
Question66:-If a block can be placed in a limited set of places in the cache, the cache is said to be

A:-Fully associative

B:-Set associative

C:-Direct mapped

D:-Restricted mapped

Correct Answer:- Option-B
Question67:-Another way of writing the instructions, SUB #5, R1 is

A:-SUB [5], [R1L

B:-SUBI 5, R1;

C:-SUBIME 5, [R1];

D:-There is no other way

Correct Answer:- Option-B
Question68:-Consider an unpipelined processor and has a 1 ns clock cycle and that it uses 4 cycles for ALU operations and
branches, and 5 cycles for memory operations. Assume that the relative frequencies of these operations are 40%, 20% and
40% respectively. Suppose that due to clock skew and setup, pipelining the processor adds 0.2 ns of overhead to the clock.
Ignoring any latency impact, how much speedup in the instruction execution rate will we gain from the pipeline?

A:-3.7 times

B:-5.8 times

C:-2.6 times

D:-6.5 times

Correct Answer:- Option-A
Question69:-BIOS {Basic Input Output System) resides in

A:-RAM

B:-ROM

C:-Cache

D:-CPU

Correct Answer:- Option-B
Question70:-The address of the instruction following the CALL instructions stored 17/0೧ (೧6

A:-stack pointer

B:-instruction counter

C:-program counter

D:-stack

Correct Answer:- Option-D
Question71:-In Process Scheduling, which of the following does not belong to a scheduler?

A:-Medium Term Scheduler

B:-Short Term Scheduler

C:-Long Term Scheduler

D:-Average Term Scheduler

Correct Answer:- Option-D
Question72:-Consider the following set of processes, with the length of the CPU-burst time and process arrival time is given
in milliseconds. Calculate the average waiting time for the Preemptive Shortest Job First scheduling algorithm.

Process Burst Time Amival Time

P1 19 0
P2 3 1
P3 6 2

A:-3.67 ms
:-2.34 5

:-5.67 ೧5
D:-7.34 ms
Correct Answer:- Option-A

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HEAD OF SECTION COMPUTER ENGINEERING TECHNICAL EDUCATION Medium of Question: English : Video