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Below are the scanned copy of Kerala Public Service Commission (KPSC) Question Paper with answer keys of Exam Name 'INSTRUCTOR GR I ELECTRONICS ENGINEERING COLLEGES TECHNICAL EDUCATION' And exam conducted in the year 2014. And Question paper code was '155/2014'. Medium of question paper was in Malayalam or English . Booklet Alphacode was 'A'. Answer keys are given at the bottom, but we suggest you to try answering the questions yourself and compare the key along wih to check your performance. Because we would like you to do and practice by yourself.
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The impulse response of a linear time invariant filter matched to an input signal is
(ക) input signal itself
(B) delayed version of the input
(C) time reversed and delayed version of input
(D) delayed input multiplied with a constant
If the input to a stable linear time invariant filter is stationary process then the output of the
filter is
(ಗಿ) ergodic (8) non stationary (3) random (D) stationary
A stack is :
(A} an 8 bit register in the microprocessor
(B) a 16 bit register in the microprocessor
(€) aset of memory locations in R/W memory reserved for storing information temporarly
during the execution of a program
(D) a 16 bit memory address stored in the program counter |
The OUT instruction :
(A) sends the data from register to output port
(8) sends the data from accumulator to output port
{C) sends data from memory location to output port
(D) sends the flag register content to accumulator
Consider an inverting amplifier configuration using op-amp with slew rate 1 V/us. The
value of resistors used in the circuit is R=R,=10 k{2, What is the shortest interval of time
that the input pulse could rise to 5 V wi lrlmul exceeding the amplifier's slew rate ?
(ಗಿ) 1ps (೧) 10 ps (ய) 0.1 ps (D) 5ps
A CMOS inverter can be formed from the proper connection of NMOS transistor Q; and
PMOS transistor Q,. The connection will be (power supply connection, properly given) :
(ಗಿ) ಟ್ರಿ ಖರೆ Q, parallel, i/p to gate of both o/p drain of both, supply to drain
(8) Q, and Q, parallel, i/p to gate of both o/ p drain of Q,
(ल) இ கால்டு, series, drain of Q, to drain of Q;, i/p to gate of both, o/p from drain.
Supply to source of Q,
(D) Q, and Q, in series, supply to source of Qy, i/p to gate of both, o/p from drain
Wire ANDing is possible with :
(A} Schottky TTL (18) Standard TTL
(C) Totem pole output (D) Open collector output
155/2014 10 A