27.

28.

29.

30.

31.

32.

33.

051/23

The steps involved in the FPGA implementation process are Mapping, Translate,
Place and Route. Arrange these implementation steps in the sequence they are
performed.

A) Translate, Place, Mapping and Route
B) Translate, Place, Route and Mapping
C) Translate, Mapping, Place and Route
D) Mapping, Translate, Place and Route

The Boolean expression y(A, B, C) = A + BC is to be realized using 2-input gates of
only one type. What is the minimum number of gates required for realization ?

A) 1 B) 3 0) 2 D) 4 or more

Find the complement of the expression y(A, B, C) = ABC + ABC + ABC + ABC
A) (A+B) (A+C) B) (A+B) (A+C)
C) (A+B) (A+C) D) (A+B) (A+C)

Measuring units of the figure of merit
A) Pico newton B) Pico watts
C) Pico joules D) Pico pascal

The number of distinct Boolean expressions of 3 variables
A) 8 B) 256 C) 128 D) 64

A certain JK FF has thy = 10 ns. The largest MOD counter that can be constructed
from such FFs and still operate up to 20 MHz is

A) 32 B) 64 C) 16 D) 8

Among the digital |C-families, which of the following statements are false ?
i. ECLis a non-saturated logic family.

ii. HTL has the biggest noise margin.

iii. CMOS has the Highest fanout.

A) Only ii B) i and ii

C) ii and iii D) None