76. The following circuit has :

Vi

IR ‏ا‎ ” +

@ Unity gain

Gi) Infinite gain

മ) High input impedance

(iv) High output impedance

(v) Zero phase shift

(vi) 180° phase shift
Which of above statements are correct?
(^) Only 0), Gii) and (vi) (B) Only (0, (11) ೩೧೮ (೪)
(C) Only Gi), (iv) and (vi) (D) Only (ii), (ii) and (v)

77. To avoid race around condition occurring in J-K flipflop :

(A) Propagation delay must be equal to clock pulse duration and clock time period

(B) Propagation delay should be less than clock pulse duration and more than clock
time period

(C) Propagation delay should be more than clock pulse duration and less than clock
time period

(D) Propagation delay should be equal to clock pulse duration and more than clock
time period

78. A 5 Bit synchronous counter uses flip-flops with propagation delay time of 20 ns each. The
maximum possible time required for change of state will be :

(A) 40ns (3) 20 78
(0 80 "5 (D) 100 75

79. Which of the following statement about multiplexer is correct?
(A) A multiplexer is also called a data distributor and parallel to serial converter
(B) A16:1 multiplexer can be implemented using four 4 : 1 multiplexers
( Two 2: 1MUXare required to implement universal gates
(D) All the above are correct

080/2023 18 A