58.

59.

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63.

64.

For the 8279 programmable keyboard/display controller, in the —————— mode, the key
matrix can be interfaced using either encoded or decoded scans.

(^) Interrupt Mode ൯) 70116431066
(C) Scanned Keyboard Mode (D) Scanned Sensor Matrix Mode

A RAM chip has a capacity of 1024 words of 8 bits each (1K x 8). The number of 2 x 4
decoders with enable line needed to construct a 16K x 16 RAM from 1K x 8 RAM is:

(A) 4 © 5
(C) 6 (D) None of the above

The reason for performing Register Renaming in pipelined processors is :
‏(ھ)‎ It is an alternative to register allocation at compile time
(B)_ It is done as part of address translation
(0) It is done for efficient access to function parameters and local variables

(D) It is done to eliminate output dependences and antidependences between
instructions

The performance of pipelined processor is badly affected if :
(൧) The pipeline stages have different delays
(B) Consecutive instructions are dependent on each other
(C) The pipeline stages share a single hardware resource
(1) All of the above

Tn an instruction execution pipeline, the earliest that the data TLB (Translation Look a side
Buffer) can be accessed is :

(A) _ before effective address calculation has started
(B) during effective address calculation

(C) after effective address calculation has completed
(D) after data cache lookup has completed

Increasing the RAM of a computer typically increases the performance because :
(A) Virtual Memory increases (B) Fewer Page Faults occur
(C) Larger RAMs are faster (D) All of the above

Consider a direct mapped cache of size 32 KB with block size 32 bytes. The CPU generates 32
bit addresses. The number of bits needed for cache indexing and the number of tag bits are
respectively, —————_ and ————__.

(A) 10,17 (B) 10, 22
(0 15,17 (0) 15, 22
11 182/2023

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