into physical addresses in a computer system?
A:-Memory Management Unit (MMU)
B:-Random Access Memory (RAM)
C:-Cache memory
D:-Input/Output (1/0) Controller
Correct Answer:- Option-A
Question28:-What advantages does DMA offer in data transfer?
A:-lt increases the size of the main memory
B:-It eliminates the need for a memory controller
6:11 reduces the need for interrupts during I/O operations
D:-It improves the performance of the CPU
Correct Answer:-Question Cancelled
Question29:-Which cache organization provides the highest level of associativity?
A:-Direct mapped cache
B:-2-way set associative cache
C:-4-way set-associative cache
D:-fully associative cache
Correct Answer:- Option-D

Question30:-Which component is responsible for prioritizing interrupts in a
computer system?

A:-CPU

B:-Memory

C:-Interrupt controller
D:-Input/output devices
Correct Answer:- Option-C

Question31:-Which type of interrupt has the highest priority is most interrupt
systems?

A:-Timer interrupt
B:-Non-maskable interrupt
C:-Software interrupt
D:-External interrupt
Correct Answer:- Option-B

Question32:-Consider a pipelined processor with the four steps instruction fetch,
Decode, Execute and Write Back. The first three steps take one clock cycle each to
complete the operation. The Execute stage depends on the instruction. The ADD
and SUB instructions requires one clock cycle, MUL requires 2 clock cycle and DIV
requires 3 clock cycles.

Operands forwarding is used in the pipelined processor. What is the number of
clock cycles taken to complete the following sequence of instructions?